1 files changed, 64 insertions, 6 deletions

diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 593e0eabd..426fc6474 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -63,16 +63,21 @@ extern void switch_mode(arm_core_t *core, uint32_t mode);
 typedef arm_core_t arm_processor;
 typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper);
 
+// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
+// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
+// support LDR/STREXD.
+static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
+
 // Exclusive memory access
 static int exclusive_detect(ARMul_State* state, ARMword addr){
-    if(state->exclusive_tag == addr)
+    if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
         return 0;
     else
         return -1;
 }
 
 static void add_exclusive_addr(ARMul_State* state, ARMword addr){
-    state->exclusive_tag = addr;
+    state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
     return;
 }
 
@@ -80,7 +85,6 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){
     state->exclusive_tag = 0xFFFFFFFF;
 }
 
-
 unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper) {
     unsigned int immed_8 = BITS(sht_oper, 0, 7);
     unsigned int rotate_imm = BITS(sht_oper, 8, 11);
@@ -943,6 +947,15 @@ typedef struct _smla_inst {
     unsigned int Rn;
 } smla_inst;
 
+typedef struct smlalxy_inst {
+    unsigned int x;
+    unsigned int y;
+    unsigned int RdLo;
+    unsigned int RdHi;
+    unsigned int Rm;
+    unsigned int Rn;
+} smlalxy_inst;
+
 typedef struct ssat_inst {
     unsigned int Rn;
     unsigned int Rd;
@@ -2399,7 +2412,25 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
     return inst_base;
 }
 
-ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index)
+{
+    arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst));
+    smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
+
+    inst_base->cond     = BITS(inst, 28, 31);
+    inst_base->idx      = index;
+    inst_base->br       = NON_BRANCH;
+    inst_base->load_r15 = 0;
+
+    inst_cream->x    = BIT(inst, 5);
+    inst_cream->y    = BIT(inst, 6);
+    inst_cream->RdLo = BITS(inst, 12, 15);
+    inst_cream->RdHi = BITS(inst, 16, 19);
+    inst_cream->Rn   = BITS(inst, 0, 4);
+    inst_cream->Rm   = BITS(inst, 8, 11);
+
+    return inst_base;
+}
 
 ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index)
 {
@@ -4613,7 +4644,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
 
             add_exclusive_addr(cpu, read_addr);
             cpu->exclusive_state = 1;
-            // TODO(bunnei): Do we need to also make [read_addr + 4] exclusive?
 
             RD = Memory::Read32(read_addr);
             RD2 = Memory::Read32(read_addr + 4);
@@ -5683,6 +5713,34 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
     }
 
     SMLALXY_INST:
+    {
+        if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+            smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
+
+            u64 operand1 = RN;
+            u64 operand2 = RM;
+
+            if (inst_cream->x != 0)
+                operand1 >>= 16;
+            if (inst_cream->y != 0)
+                operand2 >>= 16;
+            operand1 &= 0xFFFF;
+            if (operand1 & 0x8000)
+                operand1 -= 65536;
+            operand2 &= 0xFFFF;
+            if (operand2 & 0x8000)
+                operand2 -= 65536;
+
+            u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2);
+            RDLO = (dest & 0xFFFFFFFF);
+            RDHI = ((dest >> 32) & 0xFFFFFFFF);
+        }
+
+        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        INC_PC(sizeof(smlalxy_inst));
+        FETCH_INST;
+        GOTO_NEXT_INST;
+    }
 
     SMLAW_INST:
     {
@@ -6133,7 +6191,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
             if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
                 remove_exclusive(cpu, write_addr);
                 cpu->exclusive_state = 0;
-                // TODO(bunnei): Remove exclusive from [write_addr + 4] if we implement this in LDREXD
 
                 Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]);
                 Memory::Write32(write_addr + 4, cpu->Reg[inst_cream->Rm + 1]);
@@ -6265,6 +6322,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
             addr = RN;
             unsigned int value = Memory::Read8(addr);
             Memory::Write8(addr, (RM & 0xFF));
+            RD = value;
         }
         cpu->Reg[15] += GET_INST_SIZE(cpu);
         INC_PC(sizeof(swp_inst));