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author | bunnei <bunneidev@gmail.com> | 2017-10-10 05:56:20 +0200 |
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committer | bunnei <bunneidev@gmail.com> | 2017-10-10 05:56:20 +0200 |
commit | b1d5db1cf60344b6b081c9d03cb6ccc3264326cd (patch) | |
tree | fde377c4ba3c0f92c032e6f5ec8627aae37270ef /src/core/arm/dyncom/arm_dyncom.cpp | |
parent | loader: Various improvements for NSO/NRO loaders. (diff) | |
parent | Merge pull request #2996 from MerryMage/split-travis (diff) | |
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Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom.cpp')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 99758fc2a..5ebf7a2f1 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -29,6 +29,10 @@ void ARM_DynCom::SetPC(u64 pc) { state->Reg[15] = pc; } +void ARM_DynCom::PageTableChanged() { + ClearInstructionCache(); +} + u64 ARM_DynCom::GetPC() const { return state->Reg[15]; } @@ -41,6 +45,13 @@ void ARM_DynCom::SetReg(int index, u64 value) { state->Reg[index] = value; } +const u128& ARM_DynCom::GetExtReg(int index) const { + return {}; +} + +void ARM_DynCom::SetExtReg(int index, u128& value) { +} + u32 ARM_DynCom::GetVFPReg(int index) const { return state->ExtReg[index]; } @@ -80,12 +91,6 @@ VAddr ARM_DynCom::GetTlsAddress() const { void ARM_DynCom::SetTlsAddress(VAddr /*address*/) { } -void ARM_DynCom::AddTicks(u64 ticks) { - down_count -= ticks; - if (down_count < 0) - CoreTiming::Advance(); -} - void ARM_DynCom::ExecuteInstructions(int num_instructions) { state->NumInstrsToExecute = num_instructions; @@ -93,7 +98,7 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) { // executing one instruction at a time. Otherwise, if a block is being executed, more // instructions may actually be executed than specified. unsigned ticks_executed = InterpreterMainLoop(state.get()); - AddTicks(ticks_executed); + CoreTiming::AddTicks(ticks_executed); } void ARM_DynCom::SaveContext(ThreadContext& ctx) { |