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| author | Lioncash <mathew1800@gmail.com> | 2014-12-23 05:43:14 +0100 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2014-12-23 05:52:05 +0100 |
| commit | 6446331938c4d7c5bc4f54bc2b973b3eb43d7852 (patch) | |
| tree | 13db7f1f7b616b3751b7d6d6dcb3a7602a60b45b /src/core/arm/interpreter | |
| parent | armemu: Fix SEL (diff) | |
| download | yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar.gz yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar.bz2 yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar.lz yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar.xz yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.tar.zst yuzu-6446331938c4d7c5bc4f54bc2b973b3eb43d7852.zip | |
Diffstat (limited to 'src/core/arm/interpreter')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 81a4fdb92..e69789142 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp @@ -6209,16 +6209,23 @@ L_stm_s_takeabort: s16 rn_lo = (state->Reg[rn_idx]); s16 rn_hi = (state->Reg[rn_idx] >> 16); - if (rn_lo > max) + if (rn_lo > max) { rn_lo = max; - else if (rn_lo < min) + state->Cpsr |= (1 << 27); + } else if (rn_lo < min) { rn_lo = min; + state->Cpsr |= (1 << 27); + } - if (rn_hi > max) + if (rn_hi > max) { rn_hi = max; - else if (rn_hi < min) + state->Cpsr |= (1 << 27); + } else if (rn_hi < min) { rn_hi = min; + state->Cpsr |= (1 << 27); + } + ARMul_CPSRAltered(state); state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16); return 1; } @@ -6350,16 +6357,23 @@ L_stm_s_takeabort: s16 rn_lo = (state->Reg[rn_idx]); s16 rn_hi = (state->Reg[rn_idx] >> 16); - if (max < rn_lo) + if (max < rn_lo) { rn_lo = max; - else if (rn_lo < 0) + state->Cpsr |= (1 << 27); + } else if (rn_lo < 0) { rn_lo = 0; + state->Cpsr |= (1 << 27); + } - if (max < rn_hi) + if (max < rn_hi) { rn_hi = max; - else if (rn_hi < 0) + state->Cpsr |= (1 << 27); + } else if (rn_hi < 0) { rn_hi = 0; - + state->Cpsr |= (1 << 27); + } + + ARMul_CPSRAltered(state); state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF); return 1; } |