2 files changed, 62 insertions, 15 deletions

diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 98d825272..4cd8fe6ac 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -1427,6 +1427,13 @@ typedef struct _blx_1_thumb {
 	unsigned int instr;
 }blx_1_thumb;
 
+typedef struct _pkh_inst {
+	u32 Rm;
+	u32 Rn;
+	u32 Rd;
+	u8 imm;
+} pkh_inst;
+
 typedef arm_inst * ARM_INST_PTR;
 
 #define CACHE_BUFFER_SIZE	(64 * 1024 * 2000)
@@ -2376,8 +2383,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
 	}
 	return inst_base;
 }
-ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("PKHBT"); }
-ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("PKHTB"); }
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index)
+{
+	arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
+	pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
+
+	inst_base->cond = BITS(inst, 28, 31);
+	inst_base->idx = index;
+	inst_base->br = NON_BRANCH;
+	inst_base->load_r15 = 0;
+
+	inst_cream->Rd = BITS(inst, 12, 15);
+	inst_cream->Rn = BITS(inst, 16, 19);
+	inst_cream->Rm = BITS(inst, 0, 3);
+	inst_cream->imm = BITS(inst, 7, 11);
+
+	return inst_base;
+}
+
+ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index)
+{
+	return INTERPRETER_TRANSLATE(pkhbt)(inst, index);
+}
+
 ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
 {
 	arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst));
@@ -5659,8 +5688,34 @@ unsigned InterpreterMainLoop(ARMul_State* state)
 		FETCH_INST;
 		GOTO_NEXT_INST;
 	}
+
 	PKHBT_INST:
+	{
+		INC_ICOUNTER;
+		if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+			pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
+			RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000);
+		}
+		cpu->Reg[15] += GET_INST_SIZE(cpu);
+		INC_PC(sizeof(pkh_inst));
+		FETCH_INST;
+		GOTO_NEXT_INST;
+	}
+
 	PKHTB_INST:
+	{
+		INC_ICOUNTER;
+		if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+			pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
+			int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
+			RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
+		}
+		cpu->Reg[15] += GET_INST_SIZE(cpu);
+		INC_PC(sizeof(pkh_inst));
+		FETCH_INST;
+		GOTO_NEXT_INST;
+	}
+
 	PLD_INST:
 	{
 		INC_ICOUNTER;
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 2873da897..9c6602f09 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -3100,7 +3100,6 @@ mainswitch:
                     break;
 
                 case 0x68:	/* Store Word, No WriteBack, Post Inc, Reg.  */
-                    //ichfly PKHBT PKHTB todo check this
                     if ((instr & 0x70) == 0x10) { //pkhbt
                         u8 idest = BITS(12, 15);
                         u8 rfis = BITS(16, 19);
@@ -3109,18 +3108,11 @@ mainswitch:
                         state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
                         break;
                     } else if ((instr & 0x70) == 0x50) { //pkhtb
-                        const u8 rd_idx = BITS(12, 15);
-                        const u8 rn_idx = BITS(16, 19);
-                        const u8 rm_idx = BITS(0, 3);
-                        const u8 imm5 = BITS(7, 11);
-
-                        ARMword val;
-                        if (imm5 >= 32)
-                            val = (state->Reg[rm_idx] >> 31);
-                        else
-                            val = (state->Reg[rm_idx] >> imm5);
-
-                        state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
+                        u8 rd_idx = BITS(12, 15);
+                        u8 rn_idx = BITS(16, 19);
+                        u8 rm_idx = BITS(0, 3);
+                        u8 imm5 = BITS(7, 11) ? BITS(7, 11) : 31;
+                        state->Reg[rd_idx] = ((static_cast<s32>(state->Reg[rm_idx]) >> imm5) & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
                         break;
                     } else if (BIT (4)) {
 #ifdef MODE32