summaryrefslogtreecommitdiffstats
path: root/src/video_core/vertex_shader.h
diff options
context:
space:
mode:
authorTony Wasserka <NeoBrainX@gmail.com>2014-08-14 23:28:55 +0200
committerTony Wasserka <NeoBrainX@gmail.com>2014-08-25 22:03:18 +0200
commit62c36a4ef0a37fe83bb8f8680f928970bead545b (patch)
treed1431dd4a6115dcb4c93abd068149a35058bfa7d /src/video_core/vertex_shader.h
parentPica/citra-qt: Replace command list view and command list debugging code with something more sophisticated. (diff)
downloadyuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar.gz
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar.bz2
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar.lz
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar.xz
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.tar.zst
yuzu-62c36a4ef0a37fe83bb8f8680f928970bead545b.zip
Diffstat (limited to 'src/video_core/vertex_shader.h')
-rw-r--r--src/video_core/vertex_shader.h78
1 files changed, 75 insertions, 3 deletions
diff --git a/src/video_core/vertex_shader.h b/src/video_core/vertex_shader.h
index 1b71e367b..f0a8a5b60 100644
--- a/src/video_core/vertex_shader.h
+++ b/src/video_core/vertex_shader.h
@@ -117,9 +117,78 @@ union Instruction {
// while "dest" addresses individual floats.
union {
BitField<0x00, 0x5, u32> operand_desc_id;
- BitField<0x07, 0x5, u32> src2;
- BitField<0x0c, 0x7, u32> src1;
- BitField<0x13, 0x7, u32> dest;
+
+ template<class BitFieldType>
+ struct SourceRegister : BitFieldType {
+ enum RegisterType {
+ Input,
+ Temporary,
+ FloatUniform
+ };
+
+ RegisterType GetRegisterType() const {
+ if (BitFieldType::Value() < 0x10)
+ return Input;
+ else if (BitFieldType::Value() < 0x20)
+ return Temporary;
+ else
+ return FloatUniform;
+ }
+
+ int GetIndex() const {
+ if (GetRegisterType() == Input)
+ return BitFieldType::Value();
+ else if (GetRegisterType() == Temporary)
+ return BitFieldType::Value() - 0x10;
+ else if (GetRegisterType() == FloatUniform)
+ return BitFieldType::Value() - 0x20;
+ }
+
+ std::string GetRegisterName() const {
+ std::map<RegisterType, std::string> type = {
+ { Input, "i" },
+ { Temporary, "t" },
+ { FloatUniform, "f" },
+ };
+ return type[GetRegisterType()] + std::to_string(GetIndex());
+ }
+ };
+
+ SourceRegister<BitField<0x07, 0x5, u32>> src2;
+ SourceRegister<BitField<0x0c, 0x7, u32>> src1;
+
+ struct : BitField<0x15, 0x5, u32>
+ {
+ enum RegisterType {
+ Output,
+ Temporary,
+ Unknown
+ };
+ RegisterType GetRegisterType() const {
+ if (Value() < 0x8)
+ return Output;
+ else if (Value() < 0x10)
+ return Unknown;
+ else
+ return Temporary;
+ }
+ int GetIndex() const {
+ if (GetRegisterType() == Output)
+ return Value();
+ else if (GetRegisterType() == Temporary)
+ return Value() - 0x10;
+ else
+ return Value();
+ }
+ std::string GetRegisterName() const {
+ std::map<RegisterType, std::string> type = {
+ { Output, "o" },
+ { Temporary, "t" },
+ { Unknown, "u" }
+ };
+ return type[GetRegisterType()] + std::to_string(GetIndex());
+ }
+ } dest;
} common;
// Format used for flow control instructions ("if")
@@ -128,6 +197,7 @@ union Instruction {
BitField<0x0a, 0xc, u32> offset_words;
} flow_control;
};
+static_assert(std::is_standard_layout<Instruction>::value, "Structure is not using standard layout!");
union SwizzlePattern {
u32 hex;
@@ -185,6 +255,8 @@ union SwizzlePattern {
// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
BitField< 0, 4, u32> dest_mask;
+ BitField< 4, 1, u32> negate; // negates src1
+
BitField< 5, 2, Selector> src1_selector_3;
BitField< 7, 2, Selector> src1_selector_2;
BitField< 9, 2, Selector> src1_selector_1;