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authorReinUsesLisp <reinuseslisp@airmail.cc>2019-11-01 08:39:48 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-12-07 02:08:22 +0100
commit36651f215a7b9bda242ebd389ef162e8381bf834 (patch)
tree65bb717c8cb0925db9834275c4f99fef9a4c0ce5 /src/video_core
parentmaxwell_3d: Add tessellation mode register (diff)
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Diffstat (limited to 'src/video_core')
-rw-r--r--src/video_core/engines/maxwell_3d.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 05d182006..dcc7cd1fe 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -654,7 +654,10 @@ public:
BitField<9, 1, u32> connected;
} tess_mode;
- INSERT_UNION_PADDING_WORDS(0x108);
+ std::array<f32, 4> tess_level_outer;
+ std::array<f32, 2> tess_level_inner;
+
+ INSERT_UNION_PADDING_WORDS(0x102);
u32 tfb_enabled;
@@ -1415,6 +1418,8 @@ ASSERT_REG_POSITION(exec_upload, 0x6C);
ASSERT_REG_POSITION(data_upload, 0x6D);
ASSERT_REG_POSITION(sync_info, 0xB2);
ASSERT_REG_POSITION(tess_mode, 0xC8);
+ASSERT_REG_POSITION(tess_level_outer, 0xC9);
+ASSERT_REG_POSITION(tess_level_inner, 0xCD);
ASSERT_REG_POSITION(tfb_enabled, 0x1D1);
ASSERT_REG_POSITION(rt, 0x200);
ASSERT_REG_POSITION(viewport_transform, 0x280);